soulchild wrote:
malmon wrote:
I've grown rather fond of SystemVerilog lately, even though I can never seem to get enough of a hang of it to start writing without referring to code I wrote before
Holy shit I have mad respect for people who can understand verilog, it still feel like black box to me until now.
It helps to understand the roles of sequential and combinational logic of finite state machines when writing sv, but yeah, it can be rather confusing to work with the language at times.
The biggest pain in the ass though is that the software required to compile it is either massively bloated, or quite hard to use.